As it is well known, power MOS devices with a breakdown voltage BV between 200 and 1000V have a high output resistance (Ron), mainly due to the resistance of the epitaxial drain layer which may be necessary to withstand high voltages, and which depends on the dopant concentration of the epitaxial layer itself.
However, the possibility is also known of obtaining power MOS devices with a low output resistance and a high breakdown voltage BV by modifying the epitaxial layer concentration.
A known MOS device meeting this need is shown in FIG. 1, globally indicated with 3. Such a MOS power device 3 is of the so called multi-drain type and it comprises a heavily doped semiconductor substrate 1, in particular of the N+ type, whereon a semiconductor epitaxial layer 2 of the same N type is formed.
The epitaxial layer 2 forms a common drain layer for a plurality of elementary units forming the MOS power device 3. Each elementary unit comprises a body region 4, in particular of the P type, formed on the epitaxial layer 2.
In the epitaxial layer 2, below each body region 4, there is a column region 5, in particular of the P type, which extends downwards for the whole thickness of the epitaxial layer 2 towards the semiconductor substrate 1.
In particular, each column region 5 is aligned and in contact with a respective body region 4 of an elementary unit of the MOS power device 3. Both the N epitaxial layer 2 of the MOS power device 3 and the column regions 5 have a constant concentration along their whole vertical extension. In particular, these column regions 5 are formed by means of P dopant implantation carried out in the epitaxial layer 2.
The MOS power device 3 also exhibits, inside the body regions 4, heavily doped source regions 6, in particular of the N type. A lateral channel region 6a of the power device 3 is then formed by a portion of the body regions 4 adjacent to the surface of the epitaxial layer 2, and between the source regions 6 and the epitaxial layer 2 itself.
The surface of the epitaxial layer 2 is then covered with a thin gate oxide layer 7 and with a polysilicon layer 8. Openings are provided in the polysilicon layer 8 and in the thin gate oxide layer 7 to expose portions of the surface of the epitaxial layer 2 aligned with each source region 6. An insulating layer 9 completely covers the polysilicon layer 8 and it partially covers the source regions 6, so as to allow a source metallic layer 10 to contact the source regions 6 and the body regions 4. A drain metallic layer 10A is also provided on the lower surface of the semiconductor substrate 1.
It is to be noted that the presence of the column regions 5 thus allows the reducing of the resistivity of the epitaxial layer 2 without decreasing the breakdown voltage BV of the MOS power device 3 as a whole. With this type of device, it is thus possible to reach a predetermined breakdown voltage BV with a resistivity of the epitaxial layer 2 lower than that used in conventional MOS devices, and, in consequence, to obtain power MOS transistors with reduced output resistance.
Moreover, as shown in FIG. 2, MOS power devices 3 formed by means of a plurality of elementary units provided with column regions 5 exhibit a breakdown voltage BV, when the resistance of the epitaxial layer 2, shown by the curve A, varies, and is lower than the so called silicon ideal limit, shown by the curve B.
To better understand the dynamics of these known devices, with reference to FIGS. 3 to 5, a method is now described by which the MOS power device 3 of the multi-drain type of FIG. 1 is formed.
In particular, on the heavily doped N+ semiconductor substrate 1 an epitaxial layer 2 is formed comprising, at the bottom, a first N epitaxial layer 2a with a dopant concentration corresponding to a resistivity ρ.
A first photolithographic mask is formed on the first epitaxial layer 2a wherein a plurality of openings are formed. Through these openings a first P dopant implant step is carried out for forming first implanted regions 5a, as shown in FIG. 3. As shown in FIG. 4, on the first epitaxial layer 2a, a second N epitaxial layer 2b is formed with a dopant concentration corresponding to the resistivity ρ.
A second mask is then formed on the second epitaxial layer 2b wherein a plurality of openings are formed aligned with the first implanted regions 5a. Through these openings a second P dopant implant step is carried out in the second epitaxial layer 2b for forming second implanted regions 5b. 
It is possible to include any number of masking steps and subsequent dopant implantation for forming a plurality of aligned implanted regions that are placed in a succession of epitaxial layers overlapped onto each other.
As shown in FIG. 5, on the second epitaxial layer 2b, a third N epitaxial layer 2c is then formed, having a third dopant concentration corresponding to the resistivity ρ.
On the third epitaxial layer 2c, a third mask is then formed wherein a plurality of openings are formed aligned with the second implanted regions 5b. Through these openings a third P+ dopant implant step is then carried out in the third epitaxial layer 2c for forming the body regions 4 of the MOS power device 3, as shown in FIG. 1.
By means of a further masking step, a further N dopant implant step is then carried out in the third epitaxial layer 2c for forming source regions 6 of the MOS power device 3 inside the body regions.
A diffusion thermal process is then carried out to make the implanted regions 5a, 5b, the body regions 4, and the source regions 6 of the MOS power device 3 diffuse so that the implanted regions 5a, 5b form a single column region 5 aligned and in electric contact with the body region 4.
The process is then continued with conventional manufacturing steps including the formation of the thin gate oxide layer 7 and the polysilicon layer 8 on the surface of the epitaxial layer 2. Openings are then provided in the polysilicon layer 8 and in the thin gate oxide layer 7 until portions of the surface of the epitaxial layer 2 aligned with each source region 6 are exposed. The insulating layer 9 is formed until it completely covers the polysilicon layer 8 and partially covers the source regions 6, so as to allow a source metallic layer 10 formed on the MOS power device 3 to contact the source regions 6 and the body regions 4. A drain metallic layer 10A is finally formed on the back surface of the semiconductor substrate 1.
It is to be noted that the presence of the column regions 5 in contact with the body regions 4 empties the drain region 2, allowing the MOS power device 3 thus formed to withstand a predetermined voltage applied from the outside to the device even in the presence of high dopant concentrations on the epitaxial layer 2.
Moreover, the breakdown voltage BV the MOS power device 3 thus obtained succeeds in withstanding varies, being the resistivity in the epitaxial layer 2 equal with the dopant concentration in the column regions 5 (which are, in the example shown in FIGS. 1 and 3-5, of the P type).
However, the area occupied by the column regions 5, useful for the cut-off step, is not used during the conduction of the MOS power device 3: the lateral widening from the column regions 5 limits the electric performances in conduction of the MOS power device 3 thus formed.
The lateral extension and the shape of the column regions 5 is however determined by the temperature used in the diffusion thermal process for the formation of the column regions 5.
To reduce the width from the column regions 5, it is then helpful to contain the thermal balance during the diffusion thermal process, thus decreasing the lateral diffusion of the implanted regions 5a and 5b in the epitaxial layers. However, to make the thermal process with limited thermal budget diffusion allows the implanted regions 5a and 5b to form a single electrically continuous P column region 5, it is helpful to reduce the thickness of each single epitaxial layer 2a, 2b wherein each of such implanted regions 5a, 5b is formed. However, reducing the thickness of each single epitaxial layer 2a, 2b decreases the thickness of the drain region 2 and thus the final breakdown voltage BV the MOS power device 3 obtained can withstand.
Using thermal processes with reduced thermal budget and thus reduced thicknesses for the drain epitaxial layer 2, to obtain MOS power devices which can withstand a predetermined voltage equal to that which can be obtained with devices formed with greater thermal budgets, the number of the epitaxial layers forming the drain epitaxial layer 2 and the relevant implant steps forming the P column regions 5 is to be increased. This approach remarkably increases the manufacturing costs of the MOS power devices 3 thus formed.
Moreover, these power devices 3, in order to operate correctly, may include an edge structure connected to the device itself.
In fact it is known that during its cut-off operation, the drain region is depleted thus an electric field is present which may not have an uniform distribution, especially in correspondence with portions of edge of the device. This type of distribution implies the presence of higher electric field values in some regions rather than in others, mainly next to edge surfaces of the device.
Thus, to reduce the electric field value in the edge portion, an implanted dedicated region of P type is formed adjacent to the edge portion of the device 3 extending in depth along the whole drain layer 2 and which contributes to make the device 3 withstand a high voltage.
Although addressing the issue of reducing the electric field value in the edge portions of the power device 3, such solution includes a properly provided implantation step.